1. Field of the Invention
The invention relates to the field of programmed and programmable logic arrays, particularly those which operate in a static mode.
2. Prior Art
Programmed logic arrays (PLAs) are well-known in the art and are commercially available. Some of these arrays employ dynamic circuitry while others operate using static circuits. The present invention grew out of the need to convert a dynamic PLA into a static PLA. (As used in this application "static" include circuits which are truly static and those which are pseudostatic).
In U.S. Pat. No. 4,728,827 there is a discussion of problems in designing a static PLA versus a dynamic PLA. One suggestion in that patent is to use a pull-up device which is always on. For example, applying this teaching to a minterm, once the minterm is pre-charged, a small device is used to compensate for leakage. In a large array, this has the disadvantage of slowing the operation of the array. This patent teaches using a delay circuit in a feedback loop to delay turning on the precharging circuit when the output of the logic gate is transitioning from high-to-low. This allows the minterm to be more quickly discharged.
As will be seen in the present invention, while used to convert a dynamic array into a static array has application to the fabrication of a static PLA. It provides a different solution for providing a fast, low power, static PLA than taught by the prior art known to the Applicant. The present invention uses a model or dummy array. While dummy arrays for PLA's are known in the prior art, they are not used in the manner of the present invention.